1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor integrated circuit and a test control method thereof.
2. Description of the Related Art
In general, a semiconductor integrated circuit includes a separate test circuit for a test as well as normal circuits performing its own functions such as storing data, and the test circuit uses a test mode signal different from a normal mode signal for the normal circuits.
Meanwhile, the semiconductor integrated circuit supports various types of test modes, such as a test mode for controlling a voltage and a test mode for compressing data, in order to increase test efficiency. The semiconductor integrated circuit includes a test mode signal generator configured to generate test mode signals for entering a specific test mode or resetting the test mode, among the test modes.
FIG. 1 is a block diagram of a test mode signal generator for generating a test mode signal.
Referring to FIG. 1, the test modes signal generator includes a decoding circuit 10 and an output circuit 20. The decoding circuit 10 is configured to decode, for example, a 6-bit test source signal TMDEC<0:5> and generate, for example, 63 (26−1) test mode group signals TMGRPi (i=1˜63), and the output circuit 20 is configured to combine the 63 test mode group signals TMGRPi and 4 test mode select signals TMSELj (j=0˜3) and output 252 (63*4) test mode signals TESTMODEij. Though FIG. 1 illustrates only the output circuit 20 including four output units 22, 24, 26, and 28 for receiving four test mode select signals TMSELj, 62 output circuits 20 each including 4 output units 22, 24, 26, and 28 are further provided, and the 63 output circuits 20 are controlled by the 63 test mode group signals TMGRPi, respectively.
Meanwhile, the number of test mode group signals TMGRPi may be typically set to 63 after decoding, because a case that the decoding result or combination result is ‘0,’ is not used.
Hereinafter, an operation of the test mode signal generator having the above-described configuration will be described with reference to FIG. 2.
FIG. 2 is a timing diagram illustrating the operation of the test mode signal generator shown in FIG. 1.
Referring to FIG. 2, when 4 test mode select signals TMSELj may be combined in a set manner, that is, one or more of the 4 test mode select signals TMSELj are activated to a logic high level, the output circuit 20 waits for an output in a state that the activated test mode signals TMSELj are latched.
In such a state, when the 6-bit test source signal TMDEC<0:5> may be combined in a set manner, the decoding circuit 10 activates one of the 63 test mode group signals TMGRPi in response to the combined 6-bit test source signal TMDEC<0:5>.
Then, only one output circuit outputs the latched test mode select signals TMSELj as the test mode signals TESTMODEij in response to the activated test mode group signal TMGRPi.
Accordingly, a semiconductor integrated circuit enters one or more test modes among four test modes belonging to a specific test mode group, in response to a test mode signal TESTMODEij which is outputted at a logic high level among the outputted four test mode signals TESTMODEij.
Then, when entering test modes belonging to another test mode group, the semiconductor integrated circuit performs a test mode rest process TMRST. When the test mode reset process TMRST is performed, the test source signal TMDEC<0:5> and the test mode select signals TMSELj are reset to a logic low level.
In such a state, the 4 test mode select signals TMSELj are generated in another combination set, the 63 output circuits wait for an output in a state that the activated test mode select signals TMSELj are latched.
Subsequently, when the 6-bit test source signal TMDEC<0:5> are generated in another combination set, the decoding circuit 10 activates another of the 63 test mode group signals TMGRPi in response to the combined 6-bit test source signal TMDEC<0:5>.
Then, another output circuit outputs the latched test mode select signals TMSELj as the test mode signals TESTMODEij in response to the activated test mode group signal TMGRPi.
Accordingly, the semiconductor integrated circuit enters one or more test modes among four test modes belonging to another test mode group in response to a test mode signal TESTMODEij which is outputted at a logic high level among the outputted 4 test mode signals TESTMODEij.
Since the semiconductor integrated circuit may generate several hundred kinds of local test mode signals TESTMODEij with a small number of global signals TMDEC<0:5>and TMSEL<0:3>, the area thereof may be reduced.
In a state of entering a test mode belonging to a specific test mode group, however, the conventional semiconductor integrated circuit may not concurrently enter a test mode belonging to another test mode group. That is, the conventional semiconductor integrated circuit should apply a new combination of the six test mode signals TMDEC<0:5> and the four test mode select signals TMSELj, in order to enter a test mode of another test mode group in a state of entering a test mode of the specific test mode group. Therefore, the test mode reset process TMRST for resetting the entered test mode should be preceded. Accordingly, as the test mode reset process TMRST should be performed, the semiconductor integrated circuit may not concurrently enter test modes belonging to different test mode groups, as shown in FIG. 3. That is, the semiconductor integrated circuit may not maintain the test modes of different test mode groups at the same time even though the time points of entering the respective test modes are different.
Furthermore, the test mode reset process TMRST may be performed by resetting the test source signal TMDEC<0:5> and the test mode select signals TMSELj, for example, changing the signals to a logic low level or maintaining the signals at a logic low level. Therefore, although the semiconductor integrated circuit may concurrently enter two or more test modes among a plurality of test modes belonging to the same test mode group, in response to a combination of the test mode select signals TMSELj, the semiconductor integrated circuit may not selectively reset the test modes during the test mode reset process TMRST.